Experience
Three years shipping performance and reliability work on FPGA design software.
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Software Engineer
Altera (formerly Intel PSG)
- Parallelized cache generation and optimized the compiled-IP caching flow for a 40% speedup in cached synthesis, and built the testing infrastructure to track runtime regressions.
- Traced a memory doubling through an event-driven GUI flow and cut usage by 50% — over 6 GB saved on benchmark customer designs, and no more GUI freezes.
- Owned the database management system — replaced a faulty locking mechanism and made it thread- and multi-process-safe, enabling new multi-process flows.
- Implemented the design-partition Preserve feature, letting users lock finished parts of a design so later compiles run proportionally faster.
- Owned the internal netlist writer and directed adding TCL, Python and VHDL output.
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Full Stack Engineer Intern
Questrade
- Built an authenticated REST endpoint in TypeScript/NestJS over an internal SQL database, and designed the OpenAPI spec for it and a sibling endpoint.
- Instrumented a high-speed messaging system to investigate dropped messages, working with other teams on fixes.
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Software Engineering Intern
Intel
- Created the internal netlist writer in C++, converting internal data structures into hardware code to verify their correctness.
- Brought a Python analytics service back online after six months down.
- Collaborated on a netlist graph visualizer that let users query custom paths through their designs.
Education
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B.A.Sc., Computer Science
McMaster University · Summa Cum Laude · GPA 11.5 / 12
Coursework: algorithms & complexity, data structures, concurrent systems, operating systems, networks & security, databases, machine learning.
Languages
C++23 · Python · Java · TypeScript · C · TCL · Perl · SQL
Tools & systems
Linux · Git · Bash · Make · NestJS